In order to build an integrated circuit, it is generally necessary to fabricate active devices on a single substrate. In addition, it is a long-standing goal in the integrated circuit industry to make the active devices as small as possible; i.e., scale the active devices. The aim of device scaling has been two-fold: (1) to increase circuit performance (increasing circuit speed); and (2) to decrease the size of the integrated circuits so as to allow an increase in the functional complexity of the circuit (i.e., make practical the fabrication of highly integrated, complex integrated circuits). Scaling down of active device sizes was a very effective means of achieving these goals. However, the scaling of active devices has become less effective, as the limitations of the circuit speed and maximum functional density come to depend more on the characteristics of the interconnects than on the scaled devices. Since current MOS and bipolar technology devices almost invariably require more than one level of interconnect, this dependency on the interconnects is more pronounced.
Before a circuit element formed in silicon or gallium arsenide can perform a useful function, it generally must be electrically connected with other elements on the same chip and most certainly must be connected with circuitry not on the same chip. An integrated circuit is by definition a number of electrically interconnected circuit elements on the same chip. Some of the interconnections are done in the silicon itself, but most are done by means of thin conductive stripes running across the top surface of the wafer.
Referring to FIG. 1, a conventional method of fabricating a via (i.e., an interconnection between a conductor in one layer with a conductor in another layer) is described. The conventional method begins with a silicon wafer, preferably with a single crystalline substrate 10. After devices are formed on the semiconductor substrate 10 in a conventional manner, a dielectric layer 12 is formed on the substrate 10. The dielectric layer 12 is composed of BPSG (borophosphosilicate glass). Next, a first conductive layer 14 is formed on the dielectric layer 12. The conductive layer 14 is typically formed by deposition of a metal such as aluminum. A first inter-metal dielectric (IMD) layer 16 is then formed over the first conductive layer 14. Typically, the first IMD layer 16 is formed by depositing an oxide.
Subsequently, a second conductive layer is formed on the first IMD layer 16. Then, standard photolithography and etching steps are performed to form a conductive line 18 (shown in cross-section) on the top surface of the first IMD layer 16. It is understood that other conductive lines or regions (not shown) are also formed in the second conductive layer. Typically, the width of the conductive lines formed in the second conductive layer are about 0.25 mm-0.7 mm.
Referring to FIG. 2, a photoresist 22 having an opening or hole is formed in a conventional manner on the second IMD layer 20. The width of the opening is the same as the conductive line 18 formed in the second conductive layer. Ideally, the hole is perfectly aligned with the conductive line 18; however, such alignment is difficult to achieve. Instead, the hole is commonly partially misaligned with the conductive line 18 as shown in FIG. 2. An anisotropic etching step is then performed to form a via hole through the second IMD layer 20 to the conductive line 18. However, because the via hole is partially misaligned with the conductive line 18, the via hole penetrates the first IMD layer 16 to the first conductive layer 14.
As shown in FIG. 3, the anisotropic etching step creates a via hole 24 with a deep trench 26 to the surface of the first conductive layer 14. Because of the added depth of the trench 26, the via hole 24 has a relatively large aspect ratio. Subsequently, the photoresist is removed and a third conductive layer 28 is deposited on the second IMD layer 20 to fill the via hole 24 and then patterned and etched to form the via. Typically, this conductive layer is a metal layer or metal stack. However, the high aspect ratio of the via hole 24 causes the third conductive layer 28 to have poor step coverage. Consequently, the metal is deposited on the side wall of the second IMD layer 20 and does not completely fill the via hole. As is well known in the art of integrated circuit fabrication, the reduced amount of metal contacting the conductive line 18 undesirably increases the resistance of the via. In the worst case, the third conductive layer 28 short circuits the first conductive layer 14 to the conductive line 18.
To overcome this problem, conventional via fabrication methods typically increase the width of the portion of the conductive line 18 where a via is to be formed to allow for misalignment of the via hole with the conductive line 18. Of course, this wider portion or border causes the conductive line 18 to undesirably occupy more area. This increased area usage can become significant in integrated circuits having a large number of vias. In addition, these wider portions cause the conductive lines in a layer to be spaced farther apart than would be necessary if the conducive lines had no wide portions for vias. Thus, the wider portions undesirably cause a limitation in the degree of scaling possible for a given process. More specifically, even if the active devices can be made smaller, the wider portions in the conductive lines needed to form vias prevent the active devices from being more closely together.